49:43 Webinare

Accelerate HPC End-to-end Software and Hardware Design Pipelines

Name: Accelerate HPC End-to-end Software and Hardware Design Pipelines
Uploaded: 2023-07-07T15:19:36.217Z
Duration: 49 min 43 s
Description: Learn how disaggregated storage with high performance and capacity-optimized options can enhance the performance of RTL source code and binaries and still keep costs down.

Learn how disaggregated storage with high performance and capacity-optimized options can enhance the performance of RTL source code and binaries and still keep costs down.

This webinar first aired on 14. Juni 2023

The first 5 minute(s) of our recorded Webinars are open; however, if you are enjoying them, we’ll ask for a little information to finish watching.

Pure//Accelerate

HPC workloads, including software development and semiconductor design (EDA), are challenged to meet razor-thin margins and shrink product pipeline cycles. Learn how disaggregated storage with high performance and capacity-optimized options can enhance the performance of RTL source code and binaries and still keep costs down. See how development tools, such as Perforce and JFrog Artifactory, can gain a significant performance and efficiency boost.

Continue Watching

We hope you found this preview valuable. To continue watching this video please provide your information below.

This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.

Ihr Browser wird nicht mehr unterstützt!

Ältere Browser stellen häufig ein Sicherheitsrisiko dar. Um die bestmögliche Erfahrung bei der Nutzung unserer Website zu ermöglichen, führen Sie bitte ein Update auf einen dieser aktuellen Browser durch.